1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a synchronous semiconductor memory device and method for operating same.
2. Description of the Related Art
As electronic systems in the field of computers, communications, and other related industries get larger and more highly functional, such systems require semiconductor memory having ever greater storage capacity at higher speeds of operation. High-speed static random access memory devices play an important role as cache memory for computer and communication applications. Because data processors operate at an extremely high-speed, it is desirable to make the cache memory operate as fast as possible to improve performance of the system. In order to improve the data transmission rates of such memories, double data rate methods, pipeline burst methods, and the like have been utilized in the art.
FIGS. 1 and 2 show, respectively, a block diagram and timing diagram of a synchronous burst memory device in accordance with the prior art, as disclosed by Leach et al. in U.S. Pat. No. 5,923,615, issued Jul. 13, 1999. In order to provide a synchronous pipeline burst memory that can operate at high clock speeds without the addition of a pipeline stage, it has been constructed with address input buffer 22, address register 24, synchronous control circuit 26, data register 28, data output buffer 30 and asynchronous (non-synchronous) memory core 40. The address register 24 latches a burst address during a first cycle, and the latched burst address is sent to an input of the asynchronous memory core 40. The memory core comprises a plurality of memory cells 52. The output data from the asynchronous memory core 40 is not latched until a third cycle of a periodic clock signal. At this time, the third cycle is generated after a second cycle of the periodic clock signal, followed again by the first cycle thereof. Such burst operation cycle systems have the advantage of guaranteeing a sensing operation between the start of the activation of word lines to the differentiation of bit lines, which is not typical of pipeline systems in general.
Pipeline burst systems suffer a disadvantage in that the data output from the memory cells at the start of an activation timing of a latch signal provided at the synchronous control circuit 26 is not latched until the third cycle of the periodic clock signal, thereby limiting speed. As a result, the cycle time tCYC is no less than the time that it takes from transmission of an external clock signal to the latching of data at the data register. Thus, if the operation cycle time exceeds a critical time interval, there may develop errors in latching data and instability of the sensing operations.
In the field related to synchronous pipeline memory devices there have been various efforts to decrease the cycle time. Description will be made on a typical pipeline operation well known in the field.
FIG. 3 is a timing diagram for illustrating a read operation of a conventional 2-stage synchronous pipeline memory device. The read operation of the 2-stage synchronous pipeline memory device will be described with reference to FIG. 3. If an external address XADD is input at the first cycle T1 of an external clock signal XCLK, an address is decoded during the first cycle T1 to shift a row-selecting signal SWL and a column-selecting signal Yi to a memory cell array. The row- and column-selecting signals are enabled to select the corresponding memory cells. The charge stored at the selected memory cell is shared with the corresponding data lines SDL and /SDL (where xe2x80x9c/xxe2x80x9d indicates the complement of x). After the charge is shared with the corresponding data lines SDL, /SDL a block sense amplifier (BSA, or the first sense amplifier) operates in response to a sense amplifier enabling signal PSA1. The sense amplifier senses and amplifies the voltage difference between the data lines and provides the information as cell data that shows information stored about a memory cell selected at a common data line, the main data lines MDL, /MDL. The cell data is latched at the data register connected at the rear stage of the output buffer through a general output buffer connected to the main data lines MDL, /MDL. The data register shifts the latched cell data to an output driver in response to a secondary clock signal, Kdata, shifted from the second cycle of the external clock signal, XCLK. Finally, the cell data is driven by the output driver to output to an external data input /output terminal.
As a result, the cycle time tCYC is determined as the time that it takes an external clock signal to start shifting until data latches at the data register. The clock to data speed, tCD, is determined as the time that cell data latched at the data register goes through the output driver outside after activation of the secondary clock signal Kdata.
Because it takes quite long for cell data to latch to the data register in the 2-stage synchronous pipeline memory device, there may be limitations in making reductions in the cycle times. Therefore, a variety of techniques have been tried to shorten the time required for data to latch to the data register after shifting of an external clock signal.
One such technique relates to a 4(+)-stage pipelines (i. e., a pipeline having four or more stages) constructed with the addition of a data register between the sense amplifier and common data line on top of the structure of a pipeline having three or more stages. However, even if the 4(+)-stage pipeline as such can make a significant reduction in operation cycle time in comparison with the structure of a 2-stage pipeline, it is still difficult to reduce the cycle time, because there will be an overlapping interval in an extremely short cycle time when both the sense amplifier enabling signal and the second clock for controlling register are simultaneously enabled. During the overlapping terminal, data glitch may consequently bring about to result in an error in the read data.
Therefore, there is a need to more efficiently control the operation of such synchronous pipeline semiconductor memory devices having more than three stages.
Disclosed is a semiconductor memory device comprising a 4(+)-stage pipeline structure having a sense amplifier responsive to a first enable signal; a data register responsive to a second enable signal for latching an output of said sense amplifier between said sense amplifier and a common data line; and a monitoring part to monitor said first and second enable signals and adapted to prevent overlapping between an enabling interval of said first enable signal and said second enable signal.
In another aspect of the invention, the monitoring part includes a latch part constructed with logic elements.
In another aspect of the invention, the latch part is a NAND gate latch including two NAND gates.
In another aspect of the invention, the first disabling circuit is additionally connected to the monitoring part for disabling the first enable signal in response to sensing data that appears at data output terminals of the sense amplifier after the first enable signal is enabled.
In another aspect of the invention, the second disabling circuit is additionally connected to the monitoring part for disabling the second enable signal in response to output data that appears at data output terminals of the common data line after the second enable signal is enabled.
Disclosed is a synchronous pipeline semiconductor memory device, comprising a memory cell array constructed with a plurality of memory cells; a sense amplifier for sensing and amplifying cell data of a selected memory cell in response to the first enable signal shifted from the first clock cycle of an external clock; a first data register is connected between an output terminal of the sense amplifier and the common data line for outputting the output data of the sense amplifier to the common data line in response to the second enable signal shifted from the second clock cycle followed by the first clock cycle; a second data register for receiving output data of an output buffer is connected to the common data line and providing the output data to an output driver in response to the third enable signal shifted from the third clock cycle followed by the second clock cycle; and a monitoring part for monitoring the first and second enable signals and then respectively shifting the calibrated first and second enable signals to the sense amplifier and the first data register, to prevent overlapping between enabling intervals of the first and second enable signals when the first and second enable signals are respectively enabled.
In another aspect of the invention, the monitoring part includes a flip-flop circuit.
In another aspect of the invention, the flip-flop circuit is a NAND gate type of a flip-flop circuit constructed with two NAND gates.
In another aspect of the invention, the first disabling circuit is additionally connected to the monitoring part for disabling the first enable signal in response to sensing data that appears at the data output terminals of the sense amplifier after the first enable signal is enabled.
In another aspect of the invention, the second disabling circuit is additionally connected to the monitoring part for disabling the second enable signal in response to output data that appears at data output terminals of the common data line after the second enable signal is enabled.
Disclosed is a method for controlling a sense amplifier and a data register of a semiconductor memory device having the structure of operating the a 4(+)-stage pipeline constructed with an addition of a data register for latching an output of the sense amplifier between sense amplifier and common data line, the method comprising preventing the first enable signal to enable the sense amplifier from being enabled at an enabling interval of the second enable signal where output data of the data register is output to the common data line; and preventing the second enable signal from being enabled at an enabling interval of the first enable signal, thereby refraining overlapping between the enabling interval of the first enable signal and that of the second enable signal.
In another aspect of the method, the first enable signal is disabled when sensing data appears at the data output terminals of the sense amplifier after enabling of the first enable signal, and the second enable signal is disabled when output data appears at the data output terminals of the common data line after enabling of the second enable signal.
Disclosed is a synchronous pipeline memory device, comprising a memory cell array constructed with a plurality of memory cells to store data, in which required signals are synchronously generated with an external clock signal and read operations are completed by a plurality of cycles before data is output through an output driver after input of an address; a clock buffer for generating the first, second, third clocks in receipt with an external clock signal; an input buffer for receiving the external address in response to the first clock; a decoder for decoding an address output from the input buffer and outputting a row selection signal and a column selection signal to the memory cell array; a block sense amplifier for sensing and amplifying data of a memory cell selected by the decoder in response to a sense amplifier enabling signal shifted during the first clock cycle of the external clock; a first data register for latching the output data of the block sense amplifier and outputting the latched output data in response to the second clock shifted during the second clock cycle followed by the first clock cycle; a second data register with an output buffer inserted for latching the data output from the first data register and for outputting the latched data in response to the third clock shifted during the third clock cycle followed by the second clock cycle; an output driver for outputting outside the data output from the second data register; and a monitoring part for monitoring the sense amplifier enabling signal and the second clock signal and respectively shifting them to the block sense amplifier and the first data register, to prevent overlapping between an enabling interval of the sense amplifier enabling signal and that of the second clock.
In another aspect of the invention, the first disabling circuit is additionally connected to the monitoring part for disabling the first enable signal in response to sensing data that appears at the data output terminals of the sense amplifier after the first enable signal is enabled.
In another aspect of the invention, the second disabling circuit is additionally connected to the monitoring part for disabling the second clock signal in response to output data that appears at data output terminals of the common data line after the second clock signal is enabled.
Disclosed is a semiconductor memory device comprising a pipeline structure; a sense amplifier responsive to a first enable signal; a data register responsive to a second enable signal for latching an output of said sense amplifier between said sense amplifier and a common data line; and a monitoring part to monitor said first and second enable signals and adapted to prevent overlapping between an enabling interval of said first enable signal and said second enable signal.